Phase lock loop circuits (PLLs) are electronic control circuits that are widely employed in radio, telecommunications, computers and other electronic applications. A few common applications of PLLs include signal demodulation, signal recovery from a noisy channel, generation of a stable frequency at multiples of an input frequency (frequency synthesis), and distribution of precisely timed clock pulses in digital logic circuits such as microprocessors. Since a single integrated circuit can provide a complete phase-locked-loop building block, the technique is widely used in modern electronic devices. These circuits can produce output frequencies from a fraction of a hertz up to many gigahertz.
FIG. 7 depicts an arrangement of functional units in a prior art PLL 700 that is configured to generate a higher frequency output signal with reference to a lower frequency input signal. The PLL 700 includes phase detector/phase frequency detector 708, a low-pass loop filter 712, voltage controlled oscillator (VCO) 716 and a frequency divider 720. An external frequency generator produces a reference input signal 704 that is applied to an input of the phase detector 708. The output of the phase detector passes through a loop filter 712 and the filtered output operates the VCO 716. The VCO 716 generates an output signal 740, which is passed to a frequency divider 720 and the output of the frequency divider 720 provides feedback to the phase detector 708. In some embodiments, the phase detector 708 is a multiplier circuit that downconverts the feedback signal to DC (0 Hz) or near DC by modulating it with the reference frequency signal. The VCO 716 is tuned to a range of frequencies corresponding to the higher frequency harmonic so the output of the PLL 740 is a higher frequency multiple of the input reference signal 704.
In situations where the PLL 700 is generating a multiplied frequency output, the higher frequency output signal 740 would not correspond to the lower-frequency input signal 704. The frequency divider 720 receives the higher frequency output 740 and generates a lower frequency output at the same frequency as the input reference signal 704 for the phase detector 708. The phase detector 708 identifies deviations between the phase of the output signal from the frequency divider 720 and the input reference signal 704. If the input reference signal and feedback signal are locked in phase, then the two signals are orthogonal to one another (separated by 90°). The phase detector 708 generates a corrected output signal in response to any errors between the phases of the input and output signals. Thus, the PLL circuit uses a negative feedback loop to correct phase differences between the input reference signal and an output signal.
PLLs that have a wide bandwidth operate with reduced phase noise due to the VCO. As used herein, the term “bandwidth” refers to a frequency that corresponds to the rate at which a PLL circuit can recover from a perturbation between the difference in the phase of the output signal and the input reference signal. A wide bandwidth enables a PLL circuit to operate more efficiently than a PLL circuit with narrower bandwidth because a wide bandwidth PLL filters noise in the output signal from the VCO noise more efficiently and hence for the same noise performance, can use a a VCO that has a higher level of phase noise. The noisier VCO devices also consume less power during operation than lower-noise VCOs that are required for use with narrower bandwidth PLL configurations. In the PLL, the phase noise VCO is a significant power consumer in a PLL, often in excess of >50% of the PLL power, and the high power consumption is needed to reduce the standalone VCO's phase noise. Additionally, a wide PLL bandwidth reduces the phenomenon of VCO pulling, which occurs when a strong RF signal that is close to the VCO frequency, such as a radio transmitter signal, changes the VCO frequency. A wide PLL bandwidth also helps the PLL transition from one frequency to another frequency very quickly.
Existing PLL circuit designs with high bandwidth often have difficulty operating in a stable manner. For example, the maximum theoretical bandwidth in a typical prior art PLL is one-half of the input reference frequency, but practical PLL embodiments must operate with much narrower frequency bandwidths (typically one-tenth of the reference frequency) because the output signal from the frequency divider is not a continuous-time phase signal but is typically sampled at discrete time intervals. For example, as depicted in FIG. 9, a high frequency VCO output signal 904 completes four cycles 908A-908D during a single cycle 912 of a lower-frequency divider that is depicted by the samplings signal 920. The lower-frequency divider samples at rising edges 924 and 928, which can only effectively identify an average for the jitter and other high-frequency characteristics of the signal 904 over four cycles instead of identifying the jitter for individual cycles of the high-frequency VCO signal 904. The lower-frequency sampling frequency 920 for the divider results in aliasing of the higher-frequency VCO signal 904 where information about phase errors that are introduced due to jitter and other signal noise is lost in the feedback signal. As is known in the art, sampling of an output signal, especially high-frequency output signals, is prone to generation of aliased output signals due to the high frequency content in the output signal from the VCO. Inaccuracies in the output of the divider due to the aliasing in the divider often accumulate to produce an unstable output signal.
To overcome limitations in bandwidth, prior art circuits often include a series of two or more PLLs to generate an output signal. FIG. 8 depicts a configuration of two PLLs 820 and 850 that are connected in series. In FIG. 8, the first PLL 820 has a bandwidth of approximately 200 kHz and the second PLL 850 has a bandwidth of approximately 5 MHz. However, requiring a series of PLLs increases the complexity of circuit design. Consequently, improvements to PLLs that enable stable operation of a single stage PLL with wide bandwidth would be beneficial.